A receiving path in which at least one gain factor is adjustable by a gain control is well known, for example as a receiving path of a direct conversion receiver.
For illustration, a block diagram of an exemplary analog direct conversion receiver 10 is presented as FIG. 1.
The depicted receiver 10 comprises a low noise amplifier (LNA) 11 for amplifying received radio frequency (RF) signals, mixers 12 for down-converting the amplified RF signals, an analog signal processing component 13 for processing the down-converted signals, analog-to-digital converters (ADC) 14 for converting the processed analog signals into digital signals, and a digital signal processing component (DSP) 15 for a further processing of the digital signals. For processing the analog down-converted signal, the analog signal processing component 13 comprises an Nth-order low-pass filter (LPF), an automatic gain control (AGC), a direct-current (DC) offset cancellation, etc. For processing the digital signal, the DSP 15 comprises a decimation stage, an LPF, etc. The output of the DSP 15 constitutes the digital baseband (BB) output.
Implementing a receiver with a direct conversion architecture has the advantage that it is cheaper than other conversion architectures, like super-heterodyne architectures, since expensive band pass filter components for an intermediate frequency (IF) are not required in a direct conversion. Moreover, the receiver can be realized as a system on chip (SoC) solution, that is, the components of the receiver can be implemented on a single chip.
The receiver 10 can be integrated for example in a mobile terminal 16 for receiving and processing RF signals transmitted by a mobile communication network.
One known problem of direct conversion receivers is the direct current (DC) offset in the base-band. In the case of a relatively high DC offset and of a high signal gain, the base-band signal may be forced out of a desired voltage range, become distorted or even be clipped.
FIG. 2 is a schematic circuit diagram of a straightforward implementation of the front end of the receiver of FIG. 1, in which possible RF coupling paths that can convert to a DC offset in the baseband are indicated. For reasons of clarity, only one of an I branch and a Q branch is illustrated. The circuit of FIG. 2 comprises an RF amplifier 21 with the LNA 11, a Gilbert cell 22 as mixers 12, and two LPF stages 25, 27 as analog baseband filter of the analog signal processing component 13. Instead of the depicted second order LPF 25, 27, a higher order LPF can be used as well.
The LNA 11 comprises two input terminals and two outputs terminals. The LNA 11 amplifies received RF signals RFin and outputs the amplified signals as voltages Urf+ and Urf−. The outputs terminals of the LNA 11 are connected to two signal input terminals of a down-conversion mixing component 23 of the Gilbert cell 22. The mixing component 23 receives via two additional input terminals alternating local oscillator signals LO+ and LO−, which enable a down-conversion of input radio frequency signals RFin. The resulting baseband signals are output as voltages Ubb+ and Ubb− via a respective output terminal.
The first output terminal of the mixing component 23 is connected via a first input terminal of the first LPF stage 25 and a resistor R1a to a first input of an operational amplifier 26 of the first LPF stage 25, and a first output of operational amplifier 26 is connected to a first output terminal of the first LPF stage 25. A capacitor C1a on the one hand and a resistor R2a on the other hand are arranged in parallel to each other between the first input and the first output of the operational amplifier 26.
The second output terminal of the mixing component 23 is connected via a second input terminal of the first LPF stage 25 and a resistor R1b to a second input of the operational amplifier 26, and a second output of the operational amplifier 26 is connected to a second output terminal of the first LPF stage 25. A capacitor C1b on the one hand and a resistor R2b on the other hand are arranged in parallel to each other between the second input and the second output of the operational amplifier 26.
The first output terminal of the first LPF stage 25 is connected via a first input terminal of the second LPF stage 27 and a resistor R3a to a first input of an operational amplifier 28 of the second LPF stage 27, and a first output of the operational amplifier 28 is connected to a first output terminal of the second LPF stage 27. A capacitor C2a on the one hand and a resistor R4a on the other hand are arranged in parallel to each other between the first input and the first output of the operational amplifier 28.
The second output terminal of the first LPF stage 25 is connected via a second input terminal of the second LPF stage 27 and a resistor R3b to a second input of the operational amplifier 28, and a second output of the operational amplifier 28 is connected to a second output terminal of the second LPF stage 27. A capacitor C2b on the one hand and a resistor R4b on the other hand are arranged in parallel to each other between the first input and the first output of the operational amplifier 28.
The two LPF stages 25, 27 apply a second order low pass filtering on the baseband signals Ubb+ and Ubb− received from the Gilbert mixer 22. The resulting low-pass filtered baseband signals are forwarded to the analog-to-digital converters 14 of FIG. 1.
In the receiver front end of FIG. 2, a DC offset at the output of the second LPF stage 27 may be created by several mechanisms. A DC offset may be created for instance by a local oscillator signal feed-through to the RF port of the mixing component 23. This coupling path is indicted by an arrow labeled “I”. Alternatively or additionally, a DC offset may be created by a local oscillator signal feed-through to the RF port of the LNA 11 and by a subsequent down-conversion to DC. This coupling path is indicted by an arrow labeled “II”. Alternatively or additionally, a DC offset may be created by an intermodulation of an interferer in adjacent channels, due to the non-linearity (IIP2, IIP3) of the LNA 11 and the Gilbert mixer 22 to DC. This coupling path is indicted by an arrow labeled “III”. Even though not indicated in the Figure, also the baseband filter blocks 25, 27 may contribute to the DC offset with their own contribution.
Altogether, the receiver may suffer from a DC offset caused by several sources. The signals from each source are amplified in the receiver path and contribute to the total DC offset of the receiver. FIG. 3 is a simplified model of the DC offset coupling and contribution to the output of the receiver path. In this model, the frequency conversion is omitted and all signals are presented as baseband equivalent signals for the sake of simplicity.
The model comprises a first summing node 31, to which the desired baseband equivalent signal RFin_eq and in addition a first equivalent disturbing DC signal Uo1 are fed. The baseband equivalent signal RFin_eq corresponds in a real system to the received radio frequency signal RFin. The signal Uo1 corresponds in a real system to a harmful RF signal, which appears as DC signal in the baseband. The output of the first summing node 31 is connected via a gain with a gain factor of A1, which is a property of the LNA 11 and the mixer 22, to a second summing node 32. A second equivalent disturbing DC signal Uo2 is equally fed to the second summing node 32. The signal Uo2 corresponds in a real system to a harmful RF signal, which appears as DC signal in the baseband. The output of the second summing node 32 is connected via a gain with a gain factor of A2, applied by the first LPF stage 25, to a third summing node 33. A third disturbing DC signal Uo3 is equally fed to the third summing node 33. The output of the third summing node 33 is connected via a gain with a gain factor of A3, applied by the second LPF stage 27, to the analog-to-digital converters 14.
The total DC offset Uoffset_out resulting at the output of the second LPF stage 27 is then given by the following equation:Uoffset_out=Uo1*A1*A2*A3+Uo2*A2*A3+Uo3*A3.
The total DC offset is thus influenced by changes in the different DC offset contributions and as well by gain changes. The DC offset contributions may vary on a sample-to-sample basis and may further depend on time, temperature, proximity, etc.
FIG. 4 is a schematic diagram illustrating a conventional DC compensation arrangement. The diagram comprises again the elements 31, 32, 33, A1, A2, A3 of the model of FIG. 3. The output of the second LPF stage 27 represented by the gain with a gain factor of A3 is connected in an analog feedback compensation loop via an integrator 41 and a summing device 42 to the second summing node 32.
In general, DC offset contributions of Uo1, Uo2 and Uo3 can thus be classified as those coupling in before the summing node 32 of the DC offset compensation, as those coupling in at the summing node 32 and those coupling in within the compensation loop, respectively. In practice, if the summing node 32 is at the mixer output, which is frequently the case, then DC contribution of Uo1 is subject to the LNA and mixer gain having a gain factor of A1 and its variations. Exemplary origins of Uo1 are local oscillator signal feed-through via the LNA 11 and/or mixer non-linearity. DC contribution Uo2 is present at the summing node 32 and is independent of variations in the LNA gain An exemplary origin of Uo2 is the undesired local oscillator signal feed-through via the RF port of the mixers 22 and subsequent down-conversion to DC via the desired mixer action or undesired non-linearity. DC contribution Uo3 occurs within the compensation loop, for example the DC offset resulting at the second filter stage 27. Usually DC contributions Uo1 and Uo2 dominate.
The integrator 41 is used for estimating the DC offset at the output of the second LPF stage 27 by integrating the output signal over time. The integration result is then summed by the summing device 42 in opposite polarity to the second summing node 32 at the output of the mixers 12 represented by the gain with a gain factor of A1. The integration result could also be summed to another suitable node in the receiver path.
The corresponding frequency response equation indicating the DC offset created at the output is then given by:U_out—dc=((RFin_eq+Uo1)*A1*A2*A3*s+Uo2*A2*A3s+Uo3*A3s)/(s+A2*A3)
The integration applied by the integrator 41 can be continuous, in particular in 3G (third generation) receivers, or synchronized, for instance to the frame rate of GSM (global system for mobile communications). The DC offset could also be estimated differently than by an integration, for example by a positive and negative peak detection, by envelope forming, by checking whether the output signal lies within a permitted range, etc.
As an alternative to the analog feedback loop, it is also known to measure the DC offset in the digital domain after the analog-to-digital converters 14 and to subtract the compensation signal either from an analogue summing node, for instance summing node 32, via a digital-to-analog converter, or from a digital signal in the digital domain. In practice, many solutions use both techniques in parallel, in particular by carrying out a coarse compensation in the analogue domain and a fine compensation in the digital domain. In FIG. 4, a dashed line indicates by way of example that a feedback signal from a digital loop may be connected to a further input of the summing device 42.
FIG. 5 is a schematic circuit diagram of the front end of a direct conversion receiver which is provided with an analog DC compensation loop. The receiver front end presented in FIG. 5 comprises the same elements as the receiver front end presented in FIG. 2. In addition, the first output of the second LPF stage 27 is connected via a resistor R5a to a first input of an operational amplifier 51 and the second output of the second LPF stage 27 is connected via a resistor R5b to a second input of the operational amplifier 51. A first output of the operational amplifier 51 is connected via a resistor R6a in addition to the first input of the operational amplifier 26 of the first LPF stage 25. A second output of the operational amplifier 51 is connected via a resistor R6b in addition to the second input of the operational amplifier 26. A capacitor C3a is arranged between the first input and the first output of the operational amplifier 51, and a capacitor C3b is arranged between the second input and the second output of the operational amplifier 51. The components 51, R5a, R5b, R6a, R6b, C3a, C3b function as inverting integrator 52, which integrates the output of the second LPF stage 27 and which provide the inverted integration result to the input of the first LPF stage 25.
In conventional DC compensation approaches, however, two problems exist. Firstly, the frequency response may be a function of the gain setting. Secondly, every time one of the gain factors A1, A2, A3 is changed, a DC step is created. This results in contradictory requirements for the DC compensation loop. On the one hand, a fast compensation loop is preferred for enabling a fast settling due to the DC steps. On the other hand, a slow compensation loop is preferred in order to avoid an impairment, namely an attenuation, of the actually received signal. Such a prolonged DC settling can cause a momentary loss of received symbols and, ideally, should be avoided.
In order to reduce the negative effect of DC steps, a binary search, the use of faster time constants during settling, etc. have been proposed.
Also, from practical implementations of the DC offset compensation loop, it is known to use large off-chip capacitors in them.